A patent-pending code family designed for fault-tolerant quantum computing at industry-leading encoding rates.
Quantum error correction is the fundamental bottleneck between today's noisy quantum processors and practical fault-tolerant quantum computing. The dominant approaches — surface codes and bivariate bicycle codes — have well-known tradeoffs between encoding rate, code distance, and hardware connectivity requirements.
Our research explores a previously unexplored region of the qLDPC code design space: high-rate codes built from structured algebraic constructions with symmetry-based design principles. The resulting codes achieve encoding rates substantially higher than published alternatives, while remaining compatible with multiple hardware platforms.
Traditional high-rate qLDPC codes trade distance for density. Our construction achieves both through concatenation with repetition-style outer codes.
Our work spans code construction, decoding, hardware integration, and fault-tolerant architecture design.
Novel qLDPC code families with high encoding rates. Systematic search across structured polynomial families, verified by exhaustive distance enumeration and certified rank computation.
Industry-standard BP-OSD decoder integration and circuit-level simulation using modern toolchains. Exhaustive distance verification across billions of error configurations.
Platform-specific implementation analysis across neutral atom, trapped ion, and superconducting hardware. Measurement protocol design and 2D planar routing optimization.
Our code family now has measured circuit-level fault-tolerant scaling under a spacetime BP-OSD decoder, validated on NVIDIA DGX Spark (GB10 Grace Blackwell) against symmetric depolarizing noise at hardware-relevant error rates.
Full measurement tables, scaling fits, and reproducibility scripts are available under appropriate non-disclosure terms for qualified technical evaluators.
Beyond simulation: our patent-protected [[18, 6, 3]] σ-cyclic CSS code is now validated on four cloud quantum platforms with cross-broker reproducibility, and the space-time BP-OSD decoder is triply validated on real-noise-model multi-round QEC syndromes.
Total cumulative cloud-hardware spend across all results above: ~$700. Compute support: IBM Quantum Open Plan (free tier), Open Quantum / Quantum Rings, AWS Activate Founders ($1K), Microsoft Founders Hub ($5K), and Quantinuum basic1 free emulator quota. Patents filed: US Provisionals 64/030,039 + 64/036,407.
We build on the modern quantum research toolchain, ensuring our work is reproducible, verifiable, and compatible with current hardware partners.
C++-speed circuit-level noise simulation
Industry-standard belief propagation + ordered statistics
Certified GF(2) rank computation
QASM circuit generation for real hardware
Our core research is protected through multiple US provisional patent filings with ongoing preparation for non-provisional and international filings.
Detailed construction data, shift-set specifications, and full benchmark tables are available under appropriate non-disclosure terms for qualified evaluators.
High-rate fault-tolerant quantum codes enable a range of near-term and next-generation applications on existing and emerging hardware.
Fermi-Hubbard model simulation and related problems in materials science, enabling error-corrected studies of high-temperature superconductivity and strongly correlated systems.
Ground-state calculations for iron-sulfur clusters, battery cathode materials, and OLED emitter excited states — within logical qubit budgets achievable on near-term hardware.
Provably unpredictable random number generation for cryptographic and regulatory applications. A demonstrated commercial use case at achievable logical qubit counts.
Technical evaluation discussions available under appropriate confidentiality terms. Reach out to explore platform fit, licensing structures, or research collaboration.
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